Microchip manufacture is a complicated process which involves the repeated coating and etching of special materials applied to a silicon disc known as a wafer. The coatings are as hard as glass and must be polished to a near-perfect surface to ensure the resultant chips will work.
Surprisingly, the methods used to polish silicon wafers come not from the high-tech world of information technology but from glass-making, explained Prof Gerry Byrne, head of the Department of Mechanical Engineering at University College Dublin and president-elect of the Institution of Engineers of Ireland. "These machines came from the glass industry but they have not yet been optimised for this technology."
The compounds used in the polishing process react chemically with the wafer surface, but this reaction is poorly understood. The polishing pads wear, slowing things down and affecting efficiency, and this also has an impact on the accuracy of the finish.
The research team includes Prof Byrne, PhD candidate Ms Brid Mullany and MSc student Mr Barry-John Hooper, who are trying to improve things by studying the wafer-polishing process as applied at Intel's microchip plant at Leixlip, Co Kildare.
The work is co-funded by Intel and Enterprise Ireland under its strategic research grants programme. It is being carried out by the advanced manufacturing science research group in the department of mechanical engineering at UCD.
"The machines and the systems need to be improved and made more efficient," Prof Byrne said. "We are trying to improve the process reliability and the accuracy of the process."
The 200mm-diameter wafers actually contain well over 100 microchips, all made together to simplify the process. Once made, the wafer is diced up into individual chips which can be mounted into their familiar rectangular heat sinks.
Manufacture starts with a silicon disc which is coated with an inter-layer dielectric, in this case silicon dioxide. The silicon dioxide layer is polished to a very smooth finish and then exposed to a lithographic process which etches the surface and leaves behind "tracks" which will make up the circuitry in the chip.
The wafer is then recoated with the inter-layer dielectric, polished and etched again. A typical memory chip might have two or three layers, explained Ms Mullany, and a logic processor could have up to five layers prepared in this stepwise fashion. Each polishing step might take about five minutes.
A key requirement of the process is ensuring a very flat surface after polishing, Prof Byrne said. A high level of "planarity" is vital, he said. "You need to have an almost perfectly flat surface because the subsequent lithography will go out of focus."
The UCD group is trying to understand a whole range of variables associated with this process including the pressure applied to the wafer surface, the structure and wear characteristics of the polishing pads and the slurries.
"A critical issue for the whole thing is the condition of the pad," Prof Byrne said. The speed and efficiency of polishing change over the life of the pad, yet it represents a consumable and so a cost in wafer manufacture.
"We are analysing the machines to establish what the weaknesses are so we can improve the level of planarity," Prof Byrne said. The team is studying the polishing machines in use at Leixlip so there is a strongly applied edge to the research effort.
UCD also links up with other groups looking at this problem, including a group working at the University of California, Berkeley. Prof Byrne and the head of the California group are in regular contact to discuss progress.